This invention relates generally to non-volatile semiconductor memories, their operation and, in particular, to the operation of memory systems that include multiple dies connected by a memory bus.
There are many commercially successful non-volatile memory products available today, which use an array of flash EEPROM cells. An example of a flash memory system is shown in FIG. 1, in which a memory cell array 1 is formed on a memory chip 12, along with various peripheral circuits such as column control circuits 2, row control circuits 3, data input/output circuits 6, etc.
One popular flash EEPROM architecture utilizes a NAND array, wherein a large number of strings of memory cells are connected through one or more select transistors between individual bit lines and a reference potential. FIGS. 2A-2B illustrate an example of a planar NAND flash memory array. In other examples, NAND strings extend in a vertical direction in what may be referred to as three dimensional (3D) memory.
Flash memory is generally arranged in blocks, with a block being the unit of erase. FIG. 3A illustrates blocks in a memory die that are arranged in two planes. Blocks in a plane share certain circuits so that only one block in a plane is accessed at a time. Multiple planes allow multiple blocks in a die to be accessed in parallel.
Multiple dies may be connected to a memory controller by a memory bus as shown in FIG. 3B. The memory controller receives data and distributes it to the dies. While such an arrangement may allow a high degree of parallelism in some conditions, delays may occur when one or more dies become busy and thus may affect write speed.